1. Field of the Invention
The present invention relates to built-in self test for integrated circuits, and more particularly to on-chip techniques for testing random access memories embedded in application specific integrated circuits.
2. Description of Related Art
The functional testing of random access memory ("RAM") requires a large number of test vectors. Compared with random logic, for example, the functional testing of RAM requires more test vectors because RAM has more possible types of faults than random logic. When embedded RAM in an application specific integrated circuit ("ASIC") is to be tested, one must consider what test patterns should be used for testing the RAM, and how to gain access to the RAM itself.
If the architecture of the ASIC includes a bus that is accessible from the ASIC pins, the issue of access is eliminated and any one of many generally known test patterns and techniques may be used in testing the embedded RAM. For example, some suitable techniques and procedures are described in Abadir and Reghbati, "Functional Testing of Semiconductor Random Access Memories," Computing Surveys, Vol. 15, No. 3, Sep. 1983, pp. 175-98.
Special techniques must be used to functionally test embedded RAM if the architecture of the ASIC does not provide access to the RAM bus from the pins of the chip. One such technique is built-in self test ("BIST"), an example of which is described generally in Scholz et al., "ASIC Implementations of Boundary-Scan and Built-In Self-Test," Journal of Semicustom ICs, Vol. 6, No. 4, 1989, pp. 30-37. Another BIST technique described in Nadeau-Dostie et al., "A Serial Interfacing Technique for Built-In and External Testing of Embedded Memories," Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, 1989, pp. 22.2.1-22.2.5, uses the serial application of externally generated test vectors
A BIST technique for testing the overall functional operation of a microprocessor system which includes RAM and PROM (programmable read only memory) is described in U.S. Pat. No. 4,433,413, issued Feb. 21, 1984 to Fasang. The technique incorporates a pseudo-random pattern generator ("PRPG"), a signature register ("SR"), supplemental control logic, serial and parallel I/O port test logic, and a LED display into the microprocessor system. Test instructions are provided in the system PROM, while test input data is provided by the test instructions and the PRPG. Test output data is processed by the SR and the system microprocessor, and the results of the test are presented on the LED display.